1. Field of the Invention
The invention relates to the field of metal plated integrated circuit regions and members.
2. Prior Art
There has been a continual effort in the semiconductor industry to produce integrated circuits which operate at higher speeds and at a lower power levels. In metal-oxide-semiconductor (MOS) fabrication, several techniques are used to provide low resistance lines and regions. In some instances, metal lines are used instead of polycrystalline silicon (polysilicon) lines since metal lines typically have a lower resistance when compared to polysilicon. In other instances, heavier doping is used, both for the polysilicon and substrate regions to provide higher conductivity. One process for forming low resistance interconnections is described in U.S. Pat. No. 4,013,489.
As will be seen, the present invention provides a process for forming self-aligned, metal plated substrate regions and adjacent polysilicon lines. In the presently preferred embodiment, tungsten is used as the metal. The specific process for forming the tungsten layer is commercially available and marketed by AMT. With this commercial process, tungsten is formed over monocrystalline silicon and polysilicon but not over silicon dioxide or silicon nitride.